Engineering students (left to right) Christina Smith, Azad Fakhari, Juan Rios, Ma Sen, Abazar Sadeghian and Eugene Cartwright discuss field programmable gate arrays in the Computer Systems Design Laboratory.
Ma Sen holds a developmental circuit board in his hands, as if he is presenting it as a gift. Built on top of the green base are ports, switches, digital chips and connectors that comprise the hardware components of the board. Sen, a doctoral student in the Computer Systems Design Laboratory, points to a silicon chip called a field programmable gate array embedded on the board.
The architecture of that computer chip lies at the heart of the research being performed by Sen and other graduate students in the university’s computer science and computer engineering department. They are working on a system that will help software designers to configure the gates in the field programmable gate array, known in the world of computing as an FPGA, to design and implement different electronic functions in a very short period of time.
As its name suggests, the chip features reprogrammable digital circuitry. It is unlike a standard microprocessor chip produced by companies such as Intel and Motorola, which has fixed gates that execute a set of functions that cannot be changed.
But a field programmable gate array has a dense array of configurable blocks of silicon that can run independently of each other and be configured and interconnected in a virtually unlimited number of organizations to best match the requirements of a specific application, said David Andrews, professor of computer science and computer engineering.
While commercially viable field programmable gate arrays have been around since the mid-1980s, only experienced hardware designers can figure out how to arrange and connect these gates to customize them for different tasks. There were only 70,000 computer hardware engineers in the United States in 2010, according to the U.S. Department of Labor. Meanwhile, there were an estimated 1.2 million professional software application developers and programmers.
“An FPGA allows you to reconfigure the gates on the chip to better support what the application wants to do,” Andrews said. “The real challenge has been making those gates accessible to programmers. Part of what we are doing in this lab is allowing software engineers to actually guide the configuration of the gates.”
Andrews has invented a system called “hthreads in the Cloud” to solve this problem. A software designer can describe a task to this system and hthreads will generate an appropriate field programmable gate array platform. Azad Fakhari demonstrated the ease and speed of hthreads by plugging some information into the hthreads website (http://hthreads.csce.uark.edu/ARCHlang/) and hitting “submit.”
Smith holds a field programmable gate array and explains to Rios how she used it to implement a datagram protocol, which uses an ethernet port to send data over an ethernet cable.
Within seconds, the downloadable components of a complete multiprocessor system on a programmable chip appear on the screen.
“You’re just a click away from having a multiprocessor system,” Fakhari said.
It would have taken someone who isn’t a hardware designer “hours and hours and hours” to perform the task, Andrews said.
“If you didn’t have this you would have to be an expert in digital design, an expert in computer architecture, computer organization and operating systems,” he said. “You would have to sit down and by hand configure millions of gates. This automates that whole process, by the click of a button.”
The five graduate students in Andrews’ lab — Sen, Fakhari, Abazar Sadeghian, Eugene Cartwright and Christina Smith — are joined by undergraduate Juan Rios, a Bodenhamer Fellow in the Honors College. The students are engaged in projects that seek to answer three questions about field programmable gate arrays: Can the underlying hardware be customized from a software program description of an application? Can the hardware self-modify as the system is running an application? What should next generation operating systems look like, and how should they be built?
Fakhari is creating a complete multiprocessor system to be put on one chip. This is called a “system on a chip” that goes into the field programmable gate array. Sen is trying to create a new vector-type processor that the Andrews team can use within its system. Sadeghian said he likes the challenge of tracking down bugs in hardware designs.
“We write some program applications to see if this hardware is doing what we expect it to do,” Sadeghian said, “and then we measure their performance to compare it with the previous hardware. This is hardware architecture.”
Smith, a master’s student, said she became fascinated by programmable computer chips as an undergraduate at the U of A. She graduated in spring 2011 with a bachelor’s of science in computer engineering.
“I’m really enjoying the work,” she said. “I’ve always thought FPGAs were really cool inventions and a really cool way for people to solve problems.”
Andrews holds the Thomas Clinton Mullins Endowed Chair in the College of Engineering. His work with FPGAs has been funded by grants from the National Science Foundation and the United States Naval Research Laboratory.
Photos by Russell Cothren